Conventionally, there are technologies for synthesizing logic circuits using a computer. For example, there is a technology for synthesizing logic circuits based on a file in which a register transfer level (RTL) is described using a hardware description language. As examples of such a hardware description language, there are a very high speed integrated circuits hardware description language (VHDL) and Verilog-HDL. In addition, in the process of synthesizing logic circuits, the timing of signals of synthesized logic circuits is analyzed. After the process of synthesizing logic circuits, there is a process of performing physical design of circuits.    Patent Literature 1: Japanese Laid-open Patent Publication No. 10-116915    Patent Literature 2: Japanese Laid-open Patent Publication No. 2005-202610    Patent Literature 3: Japanese Laid-open Patent Publication No. 09-081621
However, in the above-described conventional technologies, there is a problem in that the timing is degraded in the process of performing physical design.
For example, in the conventional technology, there are cases where the timing of internal signals in the process of performing physical design changes from the timing of internal signals analyzed in the process of synthesizing logic circuits depending on the size or the shape of the physically-designed area. In such a case, depending on the situation of a change in the timing, the process is returned to the process of synthesizing logic circuits from the process of performing physical design, again, logic replication of signals is performed in the process of synthesizing logic circuits, and the timing of internal signals is corrected so as to allow the circuit to normally operate.
As above, in the conventional technologies, even when the timing of signals is analyzed in the process of synthesizing logic circuits, there are cases where the timing of signals is degraded in the process of performing physical design depending on the size or the shape of the area of the circuit that is physically designed in the process of performing physical design. In such a case, since the process is returned to the process of synthesizing logic circuits from the process of performing physical design, there is a problem in that a loss of the process occurs.